1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, an electronic instrument containing a semiconductor integrated circuit device, and a method of testing a semiconductor integrated circuit device.
2. Description of Related Art
A built-in system of electronic instruments, e.g., portable information devices and multimedia terminals must be provided with a CPU, an LCD controller and devices having various interface functions such as a PCMCIA, a compact flash, a key board/mouse, and ISA bus subset as companion functions.
In such a built-in system, each chip having a necessary function of the aforementioned CPU and LCD controller and having a companion function and the like is sometimes integrated on one chip as an SOC (system on chip) to improve cost-efficiency.
FIG. 1 is a view for explaining measures for making an interface between two chips, A and B in an SOC (system on chip).
As shown in the figure, the interface between an A chip 10 and a B chip 20 is made by a terminal multiplexer using a selector 30 or the like. An internal signal output from the A chip 10 is input to the B chip 20 via the selector 30 (see 60 in FIG. 1).
When a plurality of chips is integrated on one chip by using the selector 30 in this manner, in addition to a simple test for each of the A chip and the B chip, a connection test between each chip in the plurality of chips is also required.
Specifically, in FIG. 1, a test is required for each of a line 40 and a line 50 as a simple test for each of the A chip and the B chip and, in addition, it is necessary to test for a line 60 as a connection test between chips. This poses the problem that an extra connection test is required in this manner, causing an increase in testing time.
Also, there exists a problem that if the internal structure of each chip is insufficiently understood, it is difficult to prepare a test vector and to test the test vector when the connection test is made.
In recent years, in particular, there has been a strong request to integrate a plurality of chips developed by different manufacturers on one chip to form an SOC (system on chip). In such a case, it is difficult to prepare a test vector considering the structures of the chips developed by other manufacturers. It is therefore desired to develop a semiconductor integrated circuit device having a structure which can ensure the operation of an SOC (system on chip) by a test for each single chip only.
The present invention has been made in view of the foregoing technical problems, and it is an objective of the present invention to provide a semiconductor integrated circuit device, an electronic instrument and a method of testing a semiconductor device which simplifies a test circuit and can decrease test loads such as the preparation of a test vector and test time when a plurality of single chips is integrated on one chip.
(1) The present invention provides a semiconductor integrated circuit device comprising:
a first semiconductor integrated circuit;
a second semiconductor integrated circuit; and
an I/O circuit connected to an external terminal,
wherein the I/O circuit receives an internal signal, which is sent from the first semiconductor integrated circuit to the second semiconductor integrated circuit, and outputs the internal signal to outside through the external terminal and also as an input to the second semiconductor integrated circuit.
For instance, a structure may be such as an internal input terminal of the I/O circuit is connected to the output of the first semiconductor integrated circuit, an internal output terminal of the I/O circuit is connected to the input of the second semiconductor integrated circuit, the I/O circuit receives the output of the first semiconductor integrated circuit through the internal input terminal and outputs to outside through the external terminal and also provides the input to the second semiconductor integrated circuit through the internal output terminal.
The present invention ensures that only an I/O circuit and an aluminum wiring suffice for the connection between chips when a plurality of semiconductor integrated circuits is integrated on one chip. This eliminates a connection test between chips which is required when these chips are connected by a selector or the like, which can greatly decrease test loads such as test time and the formation of a test vector.
In recent years, there has been a strong request to integrate a plurality of chips developed by different manufacturers on one chip to form an SOC (system on chip). In such a case, it is difficult to prepare a test vector considering the structures of the chips developed by other manufacturers. The present invention ensures an operation by only a test for each single semiconductor integrated circuit and is therefore particularly effective when separately developed semiconductor integrated circuits are integrated on one chip.
(2) The I/O circuit of the present invention may comprise:
a first buffer to which the internal signal is input; and
a second buffer connected to a signal line which connects an output of the first buffer to the external terminal,
the first buffer many include an enable terminal, and a conductive state and a nonconductive state of the first buffer may be controlled according to an enable signal received by the enable terminal, and
the second buffer may receive at least one of the internal signal and an input signal from the external terminal and may output the internal signal or the input signal as an input to the second semiconductor integrated circuit.
When the enable signal is active, the state of the first buffer can be conductive and when the enable signal is inactive, the state of the first buffer can be nonconductive.
When the first buffer is conductive, the internal signal output from the first buffer is preferably output to outside through the external terminal and to the second semiconductor integrated circuit as the input thereof. Also, when the first buffer is in the nonconductive state, the external signal input from the external terminal is preferably output as the input to the second semiconductor integrated circuit.
According to the present invention, the input to the second semiconductor integrated circuit is switched from the internal signal to the external signal and vice versa by using such simple configuration as only controlling the state of the first buffer between conductive and nonconductive. It is therefore unnecessary to provide a input circuit for testing or the like particularly. The internal signal can be input in a normal operation and a test signal can be input from outside when the second semiconductor integrated circuit is tested. For this reason, it is unnecessary to test a test input circuit and a test vector used for a single second semiconductor integrated device may be used as is. This significantly decreases the test load.
(3) In the present invention, the semiconductor integrated circuit device may further comprise an enable signal generation circuit which generates an enable signal making a state of the first buffer conductive when an output of the first semiconductor integrated circuit is tested and making the state of the first buffer nonconductive when an output of the second semiconductor integrated circuit is tested, and outputs the enable signal as an input to the enable terminal of the first buffer.
The present invention makes it possible to control the conductive and nonconductive state of the first buffer easily using the enable signal generated by the enable signal generation circuit.
(4) In the present invention,
the I/O circuit may comprise a current characteristic test circuit testing a current characteristic of the first buffer,
the current characteristic test circuit may comprise:
an current-characteristic-test-mode setting terminal TS;
a current-characteristic-test-mode input terminal TA;
a current-characteristic-test-mode enable terminal TE;
a normal mode input terminal A;
a normal mode enable terminal E;
an input signal selection circuit which selects an input from the terminal TA and an input from the terminal A according to an input from the terminal TS; and
an enable signal selection circuit which selects an input from the terminal TE and an input from the terminal E according to an input from the terminal TS,
a signal line of the internal signal output from the first semiconductor integrated circuit may be connected to the terminal A, and an output of the input signal selection circuit may be connected to an input of the first buffer, and
an output of the enable signal selection circuit may be connected to the enable terminal of the first buffer, so that the internal signal is output to outside through the external terminal and is output as an input to the second semiconductor integrated circuit.
In the I/O circuit of the present invention, a signal from the terminal TA is input to the first buffer, and the output of the first buffer is controlled according to the enable signal from the terminal TE in the current-characteristic-test-mode. Accordingly, when the test enable signal input from the terminal TE is made active in a current-characteristic-test-mode, the characteristics of the output current of the first buffer at the xe2x80x9cHxe2x80x9d level can be inspected by changing a test input signal output from the terminal TA to the xe2x80x9cHxe2x80x9d level and the characteristics of the output current of the first buffer at the xe2x80x9cLxe2x80x9d level can be measured by changing a test input signal output from the terminal TA to the xe2x80x9cLxe2x80x9d level.
Also, a high impedance state is allowed for the first buffer to measure leak current by making the test enable signal from the terminal TE inactive in the current-characteristic-test-mode.
Because the I/O circuit of the present invention includes such a current characteristic test circuit, a current characteristic test can be simply performed.
Connection between chips requires only the I/O circuit of the present invention and aluminum wiring when a plurality of semiconductor integrated circuits are integrated on one chip, by connecting the signal line of the internal signal output from the first semiconductor integrated circuit to the terminal A and by inputting the output from the first buffer to the second semiconductor integrated circuit through the second buffer. This eliminates the necessity for a connection test between chips which is required in the case of a connection using a selector or the like, with the result that the test loads such as test time and the formation of a test vector can be remarkably decreased.
There has been a strong request to integrate a plurality of chips developed by different manufacturers on one chip to form an SOC (system on chip) in recent years. In such a case, it is difficult to prepare a test vector considering the structures of the chips developed by other manufacturers. The present invention ensures an operation by only a test for each single semiconductor integrated circuit and is therefore particularly effective when separately developed semiconductor integrated circuits are integrated on one chip.
It is to be noted that such an I/O circuit including a current characteristic test circuit as that of the present invention is preferably made into a general purpose product. Because the test time and test loads in the current characteristic test and the test for a semiconductor integrated circuit device can be remarkably reduced only by wiring a necessary signal line to each input terminal of the generalized I/O circuit including the current characteristic test circuit which is made into a general purpose product.
(5) The present invention further provides a semiconductor integrated circuit device comprising:
a first semiconductor integrated circuit;
a second semiconductor integrated circuit; and
an I/O circuit connected to an external terminal,
wherein, when a first internal signal is output to the second semiconductor integrated circuit from the first semiconductor integrated circuit, the I/O circuit outputs the first internal signal to outside through an external terminal and to the second semiconductor integrated circuit as an input thereto, and
wherein, when a second internal signal is output to the first semiconductor integrated circuit from the second semiconductor integrated circuit, the I/O circuit outputs the second internal signal to outside through an external terminal and to the first semiconductor integrated circuit as an input thereto.
According to the present invention, even when internal signals are exchanged between plural semiconductor integrated circuits by using a bidirectional signal line such as a data bus, connection between chips requires only an I/O circuit and aluminum wiring, when semiconductor integrated circuits are integrated on one chip. This eliminates the necessity for a connection test between chips which is required in the case of a connection using a selector or the like, with the result that the test loads such as test time and the formation of a test vector can be remarkably decreased.
There has been a strong request to integrate a plurality of chips developed by different manufacturers on one chip to form an SOC (system on chip) in recent years and in such a case, it is difficult to prepare a test vector considering the structures of the chips developed by other manufacturers. The present invention ensures an operation by only a test for each single semiconductor integrated circuit even when internal signals are exchanged between plural semiconductor integrated circuits by using a bidirectional signal line and is therefore particularly effective when separately developed semiconductor integrated circuits are integrated on one chip.
(6) The I/O circuit of the present invention may comprise:
a first buffer having an enable terminal;
a logical sum circuit which outputs a logical sum of a first enable signal for controlling an output of the first internal signal and a second enable signal for controlling an output of the second internal signal, as an input to the enable terminal of the first buffer; and
an internal signal selection circuit which selects one of the first internal signal and the second internal signal according to the first enable signal and the second enable signal and outputs the selected one of the first internal signal and the second internal signal as an input to the first buffer, and
the first buffer may output at least one of the first internal signal and the second internal signal to outside through the external terminal according to an output from the logical sum circuit and to the first semiconductor integrated circuit or to the second semiconductor integrated circuit as an input thereto.
(7) The present invention still further provides an electronic instrument comprising any one of the aforementioned semiconductor integrated circuit devices; an input means for data to be subjected to processing by the semiconductor integrated circuit device; and an output means for the data processed by the semiconductor integrated circuit device.
This structure makes it possible to decrease the test loads, for instance, in the development of an electronic instrument which outputs given data from an output means corresponding to the input to an input means and hence an electronic instrument with improved cost-efficiency can be provided.
In recent years, many electronic instruments are also being structured by combining CPUs, LCDs and other peripheral devices which are developed by different manufacturers. In such a case, there is a strong requirement to integrate a plurality of chips, such as CPU chips and LCD controller chips, developed by different manufacturers on one chip to form an SOC (system on chip). In such a case, the present invention also ensures an operation by only a test for each single semiconductor integrated circuit and is therefore particularly effective in decreasing the test loads when an electronic instrument is structured by combining CPUs, LCDs and other peripheral devices which are developed by different manufacturers.
(8) The present invention yet further provides a method of testing a semiconductor integrated circuit device,
wherein an internal signal from a first semiconductor integrated circuit is input to a second semiconductor integrated circuit through a first buffer of an I/O circuit connected to an external terminal, and
wherein a state of the first buffer is made conductive when an output of the first semiconductor integrated circuit is tested and the state of the first buffer is made nonconductive when an input of the second semiconductor integrated circuit is tested.